| 最大源漏极电压VdsDrain-Source Voltage | -20V |
| 最大栅源极电压Vgs(±)Gate-Source Voltage | -12V |
| 最大漏极电流IdDrain Current | -500mA/-0.5A |
| 源漏极导通电阻RdsDrain-Source On-State Resistance | 1200mΩ@ VGS = -2.5V, ID = -0.4A |
| 开启电压Vgs（th）Gate-Source Threshold Voltage | -0.65~-1.5V |
| 耗散功率PdPower Dissipation | 300mW/0.3W |
| Description & Applications | Dual P-Channel, Digital FET General Description These dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor’s advanced Power Trench process that has been especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS Applications • Battery management Features • Very low level gate drive requirements allowing direct operation in 3V circuits • Compact industry standard SC70-6 surface mount package |
| 描述与应用 | 双P沟道，数字FET 概述 这些双P沟道逻辑电平增强模式MOSFET采用飞兆半导体先进的功率沟槽进程，已特别是针对减少通态电阻。该设备已被作为一个替代双极数字晶体管和小信号MOSFET专为低电压应用 应用 •电池管理 特点 •非常低的水平栅极驱动要求可直接操作3V电路 •紧凑型工业标准SC70-6表面贴装封装 |