| 逻辑类型Logic Type | 设置（预设）和复位 Set(Preset) and Reset |
| 电路数Number of Circuits | D型 D-Type |
| 输入数Number of Inputs | 差分 Differential |
| 电源电压VccVoltage - Supply | 2 |
| 静态电流IqCurrent - Quiescent (Max) | 1 |
| 输出高，低电平电流Current - Output High, Low | 150MHz |
| 低逻辑电平Logic Level - Low | 1ns |
| 高逻辑电平Logic Level - High | 正边沿 Positive Edge |
| 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL | 24mA，24mA |
| Description & Applications | 1.65 V ~ 3.6 V |
| 描述与应用 | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. • Operate From 1.65 V to 3.6 V JESD 17 • Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) • Max t pd of 5.2 ns at 3.3 V 00-V Machine Model (A115-A) • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C – 1000-V Charged-Device Model (C101) • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C |