| 描述与应用 | SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS DESCRIPTION/ORDERING INFORMATION AUP technology is the industry's lowest-power logic technology designed for use in battery-operated or battery backed-up equipment. The SN74AUP1T97 is designed for logic-level translation applications with input switching levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. The wide VCC range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and ensures normal operation between this range. Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition. The SN74AUP1T97 can be easily configured to perform a required gate function by connecting A, B, and C inputs to VCC or ground (see Function Selection table). Up to nine commonly used logic gate functions can be performed. • Available in the Texas Instruments NanoStar™ (TOP VIEW) Packages • Single-Supply Voltage Translator • 1.8 V to 3.3 V (at VCC = 3.3 V) • 2.5 V to 3.3 V (at VCC = 3.3 V) • 1.8 V to 2.5 V (at VCC = 2.5 V) DRY OR DSF PACKAGE • 3.3 V to 2.5 V (at VCC = 2.5 V) (TOP VIEW) • Nine Configurable Gate Logic Functions • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity • Ioff Supports Partial-Power-Down Mode With Low Leakage Current (0.5 µA) • Very Low Static and Dynamic Power YFP OR YZP PACKAGE Consumption (TOP VIEW) • Pb-Free Packages Available: SON (DRY or DSF), SOT-23 (DBV), SC-70 (DCK), and NanoStar WCSP • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) • Related Devices: SN74AUP1T98, SN74AUP1T57, and SN74AUP1T58 |