| 逻辑类型Logic Type | 移位寄存器 Shift Register |
| 电路数Number of Circuits | 标准 Standard |
| 输入数Number of Inputs | 1 |
| 电源电压VccVoltage - Supply | 3 |
| 静态电流IqCurrent - Quiescent (Max) | 串行至并行 Serial to Parallel |
| 输出高，低电平电流Current - Output High, Low | 2 V ~ 5.5 V |
| 低逻辑电平Logic Level - Low | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS description/ordering information (continued) These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new dataand resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. 2-V to 5.5-V VCC Operation Max tpd of 10.5 ns at 5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports |
| 高逻辑电平Logic Level - High | 8位并行输出串行移位寄存器 描述/订购信息（续） 这些设备功能和门控串行（A和B）的输入和一个异步清零（CLR）输入。门控 串行输入允许输入的数据的完全的控制权，在任一输入为低，抑制进入新的资料与复位的第一触发器在下一个时钟脉冲的低电平。 一个高层次的输入，使输入，然后确定第一个触发器的状态。在串行输入数据是可以改变的，而时钟 的高或低，提供的最小设置时间要求得到满足。时钟发生的时钟（CLK）输入低到高层次过渡。 2 V至5.5 V的VCC操作 在5 V最大TPD10.5 NS 典型的VoIP（输出地弹跳） <0.8 V在VCC =3.3 V，TA= 25°C 典型的VOHV（输出VOH冲） 2.3 V VCC= 3.3 V，TA= 25°C 支持混合模式的工作电压 所有端口 |
| 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL | |
| Description & Applications | |
| 描述与应用 | |