| 逻辑类型Logic Type | 与门 AND Gate |
| 电路数Number of Circuits | 1 |
| 输入数Number of Inputs | 2 |
| 电源电压VccVoltage - Supply | 1.65V~5.5V |
| 静态电流IqCurrent - Quiescent (Max) | 10uA |
| 输出高，低电平电流Current - Output High, Low | -32mA，32mA |
| 低逻辑电平Logic Level - Low | 0.1V~0.55V |
| 高逻辑电平Logic Level - High | 1.2V~3.8V |
| 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL | 3.7ns @ 4.5V ~ 5.5V，50pF |
| Description & Applications | LOW VOLTAGE CMOS SINGLE 2-INPUT AND GATE WITH 5V TOLERANT INPUT；FEATURES 5V TOLERANT INPUTS HIGH SPEED: tPD = 4.5ns (MAX.) at VCC = 3V LOW POWER DISSIPATION: ICC = 1µA (MAX.) at TA = 25°C POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 5.5V (1.2V Data Retention) IMPROVED LATCH-UP IMMUNITY |
| 描述与应用 | 低压CMOS单双输入与门 与5V宽容输入；特性 5V容限输入 高速：TPD = VCC=3V时的延迟时间为4.5ns（最大值） 低功耗： ICC=1μA（最大值）在TA = 25°C 掉电保护的投入 和输出 对称的输出阻抗： | IOH= IOL =24毫安（MIN）在VCC =3V 平衡传输时延： TPLH≅TPHL 工作电压范围： VCC（OPR）= 1.65V至5.5V （1.2V数据保留） 改进的锁存-抗扰度 |