| 逻辑类型Logic Type | 解码器/多路分解器 Decoder/Demultiplexer |
| 电路数Number of Circuits | 1 x 3:8 |
| 输入数Number of Inputs | 1 |
| 电源电压VccVoltage - Supply | 24mA，24mA |
| 静态电流IqCurrent - Quiescent (Max) | 单电源 Single Supply |
| 输出高，低电平电流Current - Output High, Low | 2.7 V ~ 3.6 V |
| 低逻辑电平Logic Level - Low | 3-to-8 line decoder/demultiplexer; inverting The 74LVC138A is a high-performance, low-power,low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.The 74LVC138A accepts three binary weighted address inputs (A0, A1 and A2) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7).The 74LVC138A features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.This multiple enable function allows easy parallel expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines)decoder with just four 74LVC138A ICs and one inverter.The 74LVC138A can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. • 5 V tolerant inputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Active LOW mutually exclusive outputs • Output drive capability 50 Ω transmission lines at 125 °C • Complies with JEDEC standard no. 8-1A • ESD protection: • HBM EIA/JESD22-A114-A exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to 85 °C and −40 to 125 °C. |
| 高逻辑电平Logic Level - High | 3到8号线反相解码器/解复用器; 74LVC138A是一种高性能，低功耗，低电压，Si-gate CMOS设备，最先进的CMOS兼容TTL families.The 74LVC138A优于接受三个二进制加权地址输入（A0，A1和A2）和启用时，提供8个相互排斥的低电平输出（Y0到Y7）。，74LVC138A设有三个使能输入：两个低电平有效（E1和E2）和一个高电平（E3）。每个输出将是高除非E1和E2和E3 HIGH.This多个使能功能可轻松实现并联扩容74LVC138A 1-32（5至32线）解码器，只用四个74LVC138A IC和一台变频器。 74LVC138A为8个输出多路分解器可用于通过使用作为数据输入和剩余的使能输入，作为选通信号的低电平有效使能输入。未使用的使能输入必须永久连接到适当的高或低的状态。 •5 V容限输入与5 V逻辑接口 •宽电源电压范围从1.2到3.6 V •CMOS低功耗 •直接接口TTL水平 •输入接受高达5.5 V的电压 •解复用能力 •多输入启用易于扩展 •内存芯片非常适于选译码 •互斥输出低电平 •输出驱动能力50Ω传输线在125°C •符合JEDEC标准。 8-1A •ESD保护： •HBM EIA/JESD22-A114-A超过2000 V •MM EIA/JESD22-A115-A超过200 V •指定从-40到85°C和-40至125°C。 |
| 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL | |
| Description & Applications | |
| 描述与应用 | |