| 最大源漏极电压VdsDrain-Source Voltage | |
| 最大栅源极电压Vgs(±)Gate-Source Voltage | |
| 最大漏极电流IdDrain Current | -156A |
| 源漏极导通电阻RdsDrain-Source On-State Resistance | 60mΩ@ VGS = -1.8V, ID = -1A |
| 开启电压Vgs（th）Gate-Source Threshold Voltage | -0.8V |
| 耗散功率PdPower Dissipation | |
| Description & Applications | P-Channel 1.8-V (G-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. |
| 描述与应用 | P沟道1.8-V（G-S）的MOSFET 特性 •P沟道垂直DMOS •宏模型（子电路模型） •级别3 MOS •申请线性和开关应用 •在精确-55到125°C温度范围 •模型的栅极电荷，瞬态，二极管反向恢复特性 说明 所附的SPICE模型描述了典型的电气特性的P沟道垂直DMOS。子电路模型提取和优化，在-55到125°C的温度范围下的脉冲0-V到5-V栅极驱动。该 饱和输出阻抗是最适合在靠近大门偏置阈值电压。 一种新型的栅漏反馈电容网络是用来模型栅极电荷特性，同时避免收敛困难交换C gd模型。所有模型参数值进行了优化，提供最适合的电气测量数据，并且不打算作为一个确切的设备的物理解释。 |