| 逻辑类型Logic Type | 或门 OR Gate |
| 电路数Number of Circuits | 1 |
| 输入数Number of Inputs | 2 |
| 电源电压VccVoltage - Supply | 2V~5.5V |
| 静态电流IqCurrent - Quiescent (Max) | 1uA |
| 输出高，低电平电流Current - Output High, Low | -8mA，8mA |
| 低逻辑电平Logic Level - Low | 0.3V~1.1V |
| 高逻辑电平Logic Level - High | 1.7V~4.4V |
| 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL | 7.5ns @ 5V，50pF |
| Description & Applications | single 2-input positive-or gate;Features Operating Range of 2 V to 5.5 V Max tpd of 6.5 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V Schmitt Trigger Action at All Inputs Makes the Circuit Tolerant for Slower Input Rise and Fall Time Latch-Up Performance Exceeds 250 mA Per JESD 17 |
| 描述与应用 | 单双输入正或门;特性 2 V至5.5 V的工作范围 最大5 V时为6.5 ns吨 低功耗，10μA最大ICC ±8 mA输出驱动在5 V 施密特触发器动作在所有输入使？ 电路容错输入较慢的上升和下降时间 闭锁性能超过250 mA每 JESD17 |